FPGA Center

 * Simulation Flow

 * Creating Library

 * Compiling File

 * Loading Design

 * Simulation

 * Defining Special Signal

  * Adding Breakpoint

Starting The Simulation

Open the Wave window by clicking View > Wave.


To transfer signals to the Wave window:

Select sim group in the workspace window. Right click the name of your design and click Add > Add All Signals to Wave. Thus, you have all the signals at the wave menu.


NOTE: Each signals can be transferred by one to the wave window. To  do this, click the name of the signal in the object window, then click Add to Wave> Selected Signals.


If your design is a Testbech, (i.e the behaivour of the signals are defien in the program):
Click Simulate> Run> Run  or click the Run icon on the Toolbar.


The simulation will continue in the Wave window until the time specified in the Toolbar after Run command. This time can be changed manually so that you can defien the simulation time.


You can setup the simulation time by writing run 500 (500*defined time), run 50, run 3 us, run 5 ms in the Transcript window.


To simulate the whole area selected in the Testbench:
Click Simulate> Run> Run All or click run all icon.


NOTE: If there is no command that defines the simulation time in your program (Verilog $stop statement), simulation continues forever. In order to stop the process click Break 8icon.


Click Zoom Full 10icon to see all the signals in one window.


If your design is not a Testbench, you need to define the signals now. Click the name of the signal of which you will assing a value, in the Wave window. Click the Clock, if your signal is Clock.


If your signal is another signal, click Force then enter the suitable value for you.



After entering all the values click Run icon.





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