FPGA Center



Project Flow on ModelSim

0

Creating Project

The project directory can be changed by clicking File > Change Directory.
Click File > New > Project
.

1

Write the Project Name in the opened window then press OK button.

2

Click Add Existing File in Add Items to the Project window. Click Browse button near the File Name box in the second window. Select the files to be added to your project then click Open.

3

NOTE: Question marks under the status of a file means that this file is not compiled.

4

If there are linked codes in your HDL directories, you need to compile the main code before compiling the linked code. After this you should determine the order of compiling.

NOTE: ModelSim compiles the files from top to down.

To determine the order of the compiling, click Compie>Compile Order

5

Click Auto Generate button in the Compile Order window.

6

Click Compile>Compile All in the menu.

7

Click Simulate>Start Simulation in the menu.

8

Select the directory from the library which contains the files to be simulated, then click OK.

9

10

project                                                                                                                                  Test_bench                                                                                                                                    

                                                                                                                                                                                                                                                                   

Home | Fpga | VHDL | VHDL Dictionary | Digital Design | Simulation | PCB | Examples | Contact Us
Copyright © 2010 - 2013 FPGAcenter. All Rights Reserved.