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ARCHITECTURE

This section describes the functioning and the internal structure of the design entity. It is related to the entity.  Here, it is defined wheter the design entity is behavioral, structural or data flow model.

architecture  architecture_name of  entity_name is
declarative items (signal definitions, component definitions, etc.)

begin
     architecture body
end architecture_name;

EXAMPLE (CLOCK)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CLOCK is
     generic (upper_level : integer := 3  );          
      Port ( CLK   : in  STD_LOGIC;            -- clock input
                 outp : out  STD_LOGIC);       -- clock output
end CLOCK;
--program body
architecture Behavioral of CLOCK is
signal Counter,Counter_next: std_logic_vector(upper_level -1 downto 0):= (others =>'0');
    begin
         process(CLK)
             begin
                  if CLK= '1' and CLK'event  then                        
                        Counter<=Counter_next;
                  end if;           
          end process;
          Counter_next<= Counter +1;
          CIKIS<= Counter(upper_level -1);
   end Behavioral;

DETAILED EXPLANATION

An architecture which is related to an entity, defines the internal relations of input and output ports of that entity. It consists of two sections: Declaration ve Concurrent statements.
In declaration section,:

might be defined.

Concurrent section specifies the relationship between input and output ports. Here;

can be used.

An architecture can be written in four different methods:

NOTES:

                                                                                                                                                                                                                                                                                              

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