This section describes the functioning and the internal structure of the design entity. It is related to the entity.┬á Here, it is defined wheter the design entity is behavioral, structural or data flow model.
architecture architecture_name of entity_name is
declarative items (signal definitions, component definitions, etc.)
entity CLOCK is
generic (upper_level : integer := 3 );
Port ( CLK : in STD_LOGIC; -- clock input
outp : out STD_LOGIC); -- clock output
architecture Behavioral of CLOCK is
signal Counter,Counter_next: std_logic_vector(upper_level -1 downto 0):= (others =>'0');
if CLK= '1' and CLK'event then
Counter_next<= Counter +1;
CIKIS<= Counter(upper_level -1);
An architecture which is related to an entity, defines the internal relations of input and output ports of that entity. It consists of two sections: Declaration ve Concurrent statements.
In declaration section,:
might be defined.
Concurrent section specifies the relationship between input and output ports. Here;
can be used.
An architecture can be written in four different methods: