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ATRIBUTE PREDEFINED

object'attribute_name

The user can define his/her own attribute or can use a previously defined (predefined) attribute. Predefined attributes are actually the expressions which states the function, type and range informations of any subject.

                         BIT_VECTOR(10 downto 2);
                         BIT_VECTOR(5 downto 0);
                         BIT_VECTOR(0 to 5);
                         STD_LOGIC_VECTOR(10 downto 2);
                         STD_LOGIC_VECTOR(10 to 25);

                         BIT_VECTOR(10 downto 2);
                         BIT_VECTOR(5 downto 0);
                         BIT_VECTOR(0 to 5);
                         STD_LOGIC_VECTOR(10 downto 2);
                         STD_LOGIC_VECTOR(10 to 25);

                         BIT_VECTOR(10 downto 2); Uzunluk= 9
                         BIT_VECTOR(5 downto 0) ; Uzunluk=6;
                         BIT_VECTOR(0 to 5);   Uzunluk=6; 
                         STD_LOGIC_VECTOR(10 downto 2); Uzunluk=9;
                         STD_LOGIC_VECTOR(10 to 25); Uzunluk=16;

                         BIT_VECTOR(10 downto 2);  Range= (10 downto 2)
                         BIT_VECTOR(5 downto 0); Range=(5 downto 0)
                         BIT_VECTOR(0 to 5); Range=(0 to 5)
                         STD_LOGIC_VECTOR(10 downto 2); Range=(10 downto 2)
                         STD_LOGIC_VECTOR(10 to 25); Range=(10 to 25);

                         BIT_VECTOR(10 downto 2);  Reverse Range= (2 to 10)
                         BIT_VECTOR(5 downto 0);  Reverse Range=(0 to 5)
                         BIT_VECTOR(0 to 5);  Reverse Range=(5 downto 0)
                         STD_LOGIC_VECTOR(10 downto 2);  Reverse Range=(2 to 10)
                         STD_LOGIC_VECTOR(10 to 25);  Reverse Range=(25 downto 10);

EXAMPLE 1

signal MY_VECTOR : BIT_VECTOR(10 downto 2);

http://www.fpganedir.com/vhdl_sozlugu/RES%C4%B0M/ATRIBUTE%20PREDEFINED_clip_image002_0002.jpg

EXAMPLE 2


signal MY_VECTOR : STD_LOGIC_VECTOR(0 to 15);

http://www.fpganedir.com/vhdl_sozlugu/RES%C4%B0M/ATRIBUTE%20PREDEFINED_clip_image002_0003.jpg

EXAMPLE 3


You will see two vector type variables defined and calculation of the predefined attributes of them.

variable MY_VECTOR_1: BIT_VECTOR(10 downto 0) :="11111111111";
variable MY_VECTOR_2: STD_LOGIC_VECTOR (3 to 18):=X"1111";

 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity attribute_st is
     Port ( CLK : in  STD_LOGIC);
end attribute_st;

architecture Behavioral of attribute_st is
     begin
          process(CLK)
             variable MY_VECTOR_1:BIT_VECTOR(10 downto 0):="11111111111";
             variable MY_VECTOR_2: STD_LOGIC_VECTOR (3 to 18):=X"1111";
             variable left_1, right_1, high_1, low_1, length_s_1: integer;
             variable left_2, right_2, high_2, low_2, length_s_2: integer;
            begin
                if CLK'event and CLK='1' then
                      left_1:=MY_VECTOR_1'left;
                      left_2:=MY_VECTOR_2'left;
                      right_1:=MY_VECTOR_1'right;
                      right_2:=MY_VECTOR_2'right;
                      high_1:=MY_VECTOR_1'high;
                      high_2:=MY_VECTOR_2'high;
                      low_1:=MY_VECTOR_1'low;
                      low_2:=MY_VECTOR_2'low;
                      length_s_1:=MY_VECTOR_1'length;
                      length_s_2:=MY_VECTOR_2'length;
               end if; 
     end process; 
  end Behavioral;

We get the plot below after the simulation with ModelSim.

http://www.fpganedir.com/vhdl_sozlugu/RES%C4%B0M/ATRIBUTE%20PREDEFINED_clip_image002_0004.jpg

                                                                                                           

    

                                                                                                                                    

 

                                                                                                                                                                                                                                                                   

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