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Component represents the entity-architecture pair. It appoints a sub-system that is to be called in another architecture (instantiate) hierarchically. Instantiation of a component is similar to replacing an IC to a socket on a board.

In this way, previously created programs can be used in new projects to be created.

Component Declaration

 component  component_name
     generic (  generic_name: mytype := value;
                        other generics…  );
     port (   port_name: mode := mytype;
                   other ports...    );
end component;

Instantiation of a Component

Label : component name
                   generic map ( generic_name => value,
                                              other generics… )
                   port map ( port_name> => signal_name,
                                     other ports...   );


The code that will declare a component:

library IEEE;
entity and_gate is
      Port ( in1      : in  STD_LOGIC;
                 in2      : in  STD_LOGIC;
                 output : out  STD_LOGIC);
end and_gate;
architecture Behavioral of and_gate is
        output<=in1 and in2;
   end Behavioral;

The code that will instantiate the declared component:

library IEEE;
entity component_example is
     Port ( A : in  STD_LOGIC;
               B : in  STD_LOGIC;
               C : out  STD_LOGIC);
end component_example;
architecture Behavioral of component_example is
COMPONENT and_gate
      PORT(    in1 : IN std_logic;
                      in2 : IN std_logic;         
                      output : OUT std_logic    );
  U: and_gate PORT MAP(  in1 =>A ,
                                              in2 =>B ,
                                              output => C );
end Behavioral;


A component must be declared before instantiating it. Component declaration is similar to defining the socket in the circuit board example. It means that defining the virtual interface of the design entity that will be used. In other words, component declaration is to prepare the location that the component will be replaced.

Component declaration can be done in package, design entity, architecture or block structures. Usually it is done in a package. In this way, the component becomes available for all architectures that use the same package which includes the defined components.


Architecture STRUCTURE_2 of EXAMPLE is
component XOR_4 is
   port( A,B: in BIT_VECTOR(0 to 3);            -- Component is declaring here.
               C: out BIT_VECTOR(0 to 3));        
--Component XOR_4 has  4-bit A, B inputs and a C output.
end component XOR_4;

signal S1,S2 : BIT_VECTOR(0 to 3);
signal S3 : BIT_VECTOR(0 to 3);
 -- instantiation of the component is done with a label X1. A,B ve C.                    
--   Port interfaces are associated with S1, S2 and  S3 signals.
       X1 : XOR_4 port map(S1,S2,S3);
end architecture STRUCTURE_2


Components that are declared in an architecture can be used only in that architecture.

Component must be declared before the begin expression in an architecture. In this way, the component can only be used in that architecture.

Instantiation of a Component

It is needed to use components in order to define a VHDL design hierarchy or create a netlist. Netlist is a structural definition of a design. By instantiating a component, a new hierarchical structure is created. And a new netlist is created with the linked components to each other.

Using component might be done in three ways:

Generic map (optional) is used to address the values of the generics themselves. In port map, each expression is addressed to a different signal.

Component Instantiation:

Name of an instantiated component must be same with the name of the declared component. Components can be instantiated with lists of generic and port parameters. This can be done either with positional list or named list.

1) Positional List: Parameters are listed in the order which is specified when declaring the component.


architecture Structural of ALU is
signal X,Y,S,C : bit ; -- X,Y,S and C signals are declared in ALU structure.

component HalfAdder is
    port ( In1, In2         : in bit;
              Sum, Carry : out bit);
end component HalfAdder;
  HA : HalfAdder port map (X,Y,S,C); --HalfAdder component is instantiated.
  --In1,In2,Sum  and Carry ports are instantiated as X,Y,S and C respectively.

     . . .
end architecture Structural;

2) Named List: Parameters may not be listed in a specified order. In this case, the ports should be referenced  clearly to related names.


architecture Structural of ALU is
signal X,Y,S,C : bit;
component HalfAdder is
   port (In1, In2 : in bit;
         Sum, Carry : out bit);
end component HalfAdder;
   HA : HalfAdder port map (Sum=>S, Carry=>C,  In1=>X, In2=>Y); 
--HalfAdder component is instantiated
--Names of the ports Sum, Carry, In1 and In2 are referenced here.
    . . .
end architecture Structural;

Entity Instantiation:

There is no need to declare any component every time. An entity/architecture pair might be instantiated directly. In this case, the design entity name and name of the architecture (optional) should be written in the component instantiation.


library IEEE;
entity Exm is
    Port ( A : in  STD_LOGIC;
              B : in  STD_LOGIC;
              C : out  STD_LOGIC);
end Exm;
architecture Behavioral of Exm is
       u1:entity and_gate (Behavioral) -- architecture name in the And_gate program
            port map(A,B,C);
end Behavioral;






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