

DATA TYPES
Each data type scan Â be transformed into different types by using functions
1. STD_LOGIC
It is the most commonly used data type in VHDL language. IEEE library is located in the package STD_LOGIC_1164. Although it might have 8 different values, three of them are often used: â1â, â0â and âZâ
â1â Â Â Â Â :Logic 1
â0â Â Â Â Â :Logic 0
âHâ Â Â Â :Weak 1
âLâ Â Â Â Â : Weak 0
âXâ Â Â Â :Unknown
âUâÂ Â Â Â :Undefined
âZâ Â Â Â Â :High Impedance
âDâ Â Â Â :Donât care
âWâÂ Â Â Â :Weak Unknown
2. STD_LOGIC_VECTOR
It is used to describe datas which have multiple std_logic type.
Example: â00000â, â1X00â , âUXZ0011â
3. BOOLEAN
It takes one of the values ofÂ True or False. False is the default value. Conditional expressions "<,>, <=,> =, = or / =" are used in conjunction with operators. They are defined in the Standard Package.
type boolean is (false,true);
Example:
signal CondSup : boolean;
. . .
CondSup <= true;
. . .
if CondSup then
4. INTEGER
It is a numeric type which consists of integer numbers of range from negative (2e31 1) to positive (2e31 1).
Value range and the ranking may vary depending on the user. If you assign a value to a variable outside the defined range, an error occurs.
Integers may be used for Standard operators such as addition, subtraction, multiplication, division, module. They may also used used as comparison such as greater than, equal, unequal, less thanâŠ
Example:
type Voltage_Level is range 0 to 5;
type Int_64K is range 65536 to 65535;
type WORD is range 31 downto 0;
variable akÄ±m:integer:=12;
signal temp:integer range 0 to 200;
5. NATURAL
It consists of the integer values which are greater or equal than zero.
Example:
signal counter :natural range 0 to 200;
6. POSITIVE
It consists of the integer values which are greater than zero.
signal counter :positive :=100;
7. BIT

It takes values of '0' or '1'. The dafult value of every object in Standard package is '0'. In order not to be confused with the integer ones, the logic â0â and â1â have to be used in quotation.
Example:
type bit is ('0','1');
signal BitSig1, BitSig2 : bit;
. . .
BitSig1 <= '1';
BitSig2 <= not BitSig1;
8. BIT_VECTOR
Bit_vector type is defined as an array whose each elements are bits. Size of array is determined in the declaration part. Values of arrays which is ofÂ type bit_vector have to be written in the "double quotes". Single elements of bit type have to be written in 'single quotes'.
Example:
type bit_vector is array (natural range <>) of bit;
signal DataBus : Bit_vector(7 downto 0);
signal FlagC : Bit;
DataBus(0) <= '1';
DataBus <= '0' & "111000" & FlagC;
DataBus <= ('0', others => '1');
DataBus <= DataBus(6 downto 0) & DataBus(7);
DataBus <= "01110001";
9. REA
L
It represents the real numbers.
Example:
constant Pi_number: real := 6.28318530717958647693;
constant Pi_number: real := 6.2831_8530_7179_5864_7693;
10. CHARACTER
It is defined in the Standard package. There are 256 defined characters including "=", "/=", "<', "<=", ">"and Â ">=".
11. STRING (POSITIVE)
It is a one dimensional array which consists of characters. The array size and ranking is Â determined in the declaration part. Strings are used in concatenation, aggregate or slice operations.
It is possible to compare strings by using operators "=", "/=", "<", "<=", ">" or ">=". Also they can be combined by using "&" operator.
They are written in âdouble quotesâ. They are not syntesizable. They can be used for giving a message during the simulation. (assertion)
Example:
constant Name: STRING := "FPGA";
constant Message1 : String(1 to 6) := "Center";
signal Letter1 : character;
signal Message2 : string(1 to 10);
. . .
Message2 <= Name & Message1;
12. TIME
It represents the time values of hr, min, sec, ms, us, ns, ps and fs.
They are written in âdouble quotesâ. They are not syntesizable. They can be used for giving a message during the simulation. (assertion)
Example:
constant clk_period : time := 2 us;
13. DELAY_LENGTH
It represents the time values which are equal or greater than zero.
14. COMPOSITE TYPE
It is the data type of ta objects which consit of multiple elements. There are two types of composite:"array type" and " record type".Â Elements of records may be in different types. However all elements of an array have to be in the same type.
Each array elements have an index number.
15. SIGNEDUNSIGNED
These two important types are defined in the std_logic_arith package. These types provide access to each individual bits in different numerical values, unlike integers. With this property they are similar to type bit_vector.
However, these types of signal and variable operations are defined as numeric operations in package std_arith.
Example:
type UNSIGNED is array (natural range <>) of std_logic;
type SIGNED is array (natural range <>) of std_logic;
Unsigned
It means an unsigned numerical value. The leftmost bit is the most significant bit (MSB). For example, number 8 in the decimal system is shown as UNSIGNED '("1000"). For an nbit unsigned signal or a variable, a numeric range of size (2eN 1) is assigned. For example, a 4bit variable can take numeric values up to 15.
Example:
variable VAR: UNSIGNED (1 to 10);
 10 bit number
 MSB: VAR(VARâleft) = VAR(1)
signal SIG: UNSIGNED (5 downto 0);
 6 bit number
 MSB: SIG(SIGâleft) = SIG(5)
Signed
It means an unsigned numerical value.
The leftmost bit is the sign bit. Where '1 ' indicates Â that it is a negative number and Â '0' indicates that it is a positive.
Example:
SIGNEDâ("0101")  (+5)
SIGNEDâ("1011")  (5)
For an nbit signed signal or a variable, a numeric range from (2eN) to (2eN 1) is assigned. For example, a 4bit variable can take numeric values from 8 to 7.
Example:
variable S_VAR: SIGNED (1 to 10);
 11 bit number
 sign bit: S_VAR(S_VARâleft) = S_VAR(1)
signal S_SIG: SIGNED (5 downto 0);
 6 bit number
 sign bit: S_SIG(S_SIGâleft) = S_SIG(5)
18. FLOATING POINT TYPE
It is a type of real numbers defined in a specified range. They can be used in addition, subtraction, multiplication, division, absolute value, and exponentiation functions.
Example:
type type_name Â is real_name _left_limitÂ downto real_name _right_limit ;
type type_name Â is real_name _left_limitÂ to real_name _right_limit ;
Example:
type Voltage_Level is range 5.5 to +5.5;
type Int_64K is range  65536.00 to 65535.00;