Entity defines the interface between the design and its outer environment. The input and output ports are declared in this part.
There is only one entity in each VHDL design. There may be more than one architecture or configuration, in order to control over the VHDL code easier. However, codes with one architecture, one entity an done configuration is usually used.
entity name is
port_name: mode type;
other ports... );
Entity and design entity are different concepts. The whole design Â which consist of an entity and an architecture may be names as design entity.
Entity name can consist of letters, characters and numbers provided that the name starts with a character.
EXAMPLE 1 (MULTIPLEXER)
entity MUX is
Port ( data0 : in STD_LOGIC;
data1 : in STD_LOGIC;
sel : in STD_LOGIC;
result : out STD_LOGIC );
architecture Behavioral of MUX is
with sel select
result <= data0 when '0',
data1 when '1',
'Z' when others;
EXAMPLE 2 (BCD Decoder)
entity BCD_Decoder is
BCD : in Bit_Vector (2 downto 0);
Enable : in Bit;
LED : out Std_Ulogic_Vector (3 downto 0));
constant ZERO : Std_Ulogic_Vector(3 downto 0) := "0000";
assert (BCD /= "111") report "BCD = 7 " severity note;
end entity BCD_Decoder;
LED output signal is defined as a type of "Std_Ulogic_Vector". Since it is not a standard type,
the IEEE library and "std_logic_1164" package is used. If "Bit_Vector" was used instead of "Std_Ulogic_Vector", you would not need these two lines.
Optionally, the type, subtype and the entity constants of sub-programs can be described in this section. Â Expressions defined in entity, are allowed to be used to be used in all architectures which are assigned to that entity. An architecture is the description of the interior design, and only is assigned to one entity. But more than one architecture may be assigned to a single entity.
Entity expression comes after the library and use expressions. In this way, all declarations defined in the package becomes available.
All statements that belong to an entity, are all written after the word begin. All statements here are passive, that is none of the signalâ€™s value changes. At the same time, instantiation of passive concurrent assertion and passive concurrent procedures are done here.