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EVENT

Event is an attribute that returns information about signals (such as whether that signal has changed its value or its previous value)

If the value of a signal has an event (changed its value) in the current simulation cycle, this attribute returns TRUE.
Event is an important and commonly used attribute in VHDL.

Any change on a signal can be detected by usign event.

Its function is based on checking any change on the edges of clock signal. The last change on the clock signal can be detected by using LAST_EVENT attribute.  This attribute returns the time elapsed since the previous event occurring on this signal.

When execution reaches the end of the process, the process suspends itself, and waits for another event to occur on a signal in its sensitivity list.

event

NOTES:


EXAMPLE 1


variable T: time;
begin
   b <= a after 20 ns;
   wait 50 ns;
  T := b'last_event; -- Value of T becomes 50 ns
. . .
end process;


EXAMPLE 2


process(Rst,Clk)
begin
   if Rst = '0' then
      b <= a;
  elsif CLK'event and CLK='1' then  -- The expression returns TRUE on the rising edge of the clock signal.
     a <= '1';
  end if;
end process;

If Rst is '0' vaue of “a” is assigned to “b”. If Rst is '1' and if an event occurs on the CLK signal while its value is '1', variable “a” becomes '1'.

                                                                                                           

    

                                                                                                                                    

 

                                                                                                                                                                                                                                                                   

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