FPGA Center



EXIT

Exit is used to exit the loop. If this statement contains a condition, it means that exiting from the loop depends on that condition.

After exit statement processed, the first next expression is processed. There is no necessity to use the name of the loop. If a label is not used, the inner loop ends. If you want to exit the outer loop, a label must be used.


exit;
exit loop_name;
exit loop_name when condition;

NOTE:

Exit statement is usually confused with next statement. The important point to remember is, the loop ends when you use “exit”, but the next statement is processed when you use “next” without exiting the loop.


EXAMPLE 1

Loop_1: for count_value in 1 to 10 loop
                     exit Loop_1 when reset = '1';
                       A_1: A(count_value) := '0';
                 end loop Loop_1;
          A_2: B <= A;;

In this example, reset:’1’ condition is checked in every repititions in the loop. If reset is 1, he loop ends then the A_2 labeled line is processed.  Oherwise next step in the loop is processed.


EXAMPLE 2


Loop_X: loop
           a_v := 0;
           Loop_Y:    loop
                      Exit_1:    exit Loop_X when condition_1;
                                       Output_1(a_v) := Input_1(a_v);
                                        a_v := a_v + 1;
                      Exit_2:     exit when condition_2;
           end loop Loop_Y;
           Assign_Y: B(i) <= Output_1(i) after 10 ns;
           Exit_3:    exit Loop_X when condition_3;
 end loop Loop_X;

 Assign_X: A <=B after 10 ns;

There are two nested loops (LOOP_X and LOOP_Y) in the example above. If the condition_1 is TRUE, Exit_1 is processed then LOOP_X ends. Then the next step (Assign_X) is processed.

If condition_1 becomes FALSE, the next steps are processed including condition_2.  If this condition_2  is TRUE, Exit_2 is processed then LOOP_Y which is the inner loop ends and Assign_Y is processed.

If this condition_3  is TRUE, LOOP_X ends. Since this condition is located in the outermost loop, you don’t have to write LOOP_X as label in the Exit_3 line.


EXAMPLE 3


In this example we will design an adder which will result the sum of the numbers from 1 to the last number variable. There will be a start input and program will be activated at the start signal’s rising edge.

If the last_number is 5, the sum is:

1+2+3+4+5=15

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sum is
Port ( start : in  STD_LOGIC;
          last_number : in  STD_LOGIC_VECTOR(5 downto 0);
          result : out  STD_LOGIC_VECTOR(15 downto 0) );
end sum;

architecture Behavioral of sum is
    begin
        process(start)
            variable temp:integer:=0;
            variable i:integer:=0;
            begin
                 if start ='1' and start 'event then
                     temp:=0;
                     i:=0;
                     SUM_LOOP:loop
                                                i:=i+1;
                                                temp:=temp+i;
                                                exit SUM_LOOP when i= CONV_INTEGER(last_number);
                                            end loop;
                   result<= CONV_STD_LOGIC_VECTOR(temp,16);            
              end if;
       end process;
end Behavioral;

After simulating the code with Modelsim, we will get the plot below:

1

                                                                                                           

    

                                                                                                                                    

 

                                                                                                                                                                                                                                                                   

Home | Fpga | VHDL | VHDL Dictionary | Digital Design | Simulation | PCB | Examples | Contact Us
Copyright © 2010 - 2013 FPGAcenter. All Rights Reserved.