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FOR LOOP

For loop represent the sequential statements that will be repeated.

Expressions in loops, will continue to be processed as long as condition is satisfied. Then the first statement after the end of the loop is reached.

The "for" loop is used in process, function, procedure for sequential statements. .

If you need to specify the number of expression in the loop will be repeated, "for" loop is used. Repeats within the range specified in the parameter is changed, from the left to the far right side. (Example 1)

Another for-loop is "for-generate" statements. (Example 2)

NOTE:. "Exit" expression is used in order to exit the loop. If needed it can be related with a condition.

1) FOR LOOP (Sequential Statements)

          for  variable in bottom_limit  to upper_limit [upper_limit downto bottom_limit  ] loop
                 -statements
                 -statements
           end loop;

2) FOR  GENERATE (Concurrent Statements)

 Label: for  variable in bottom_limit  to upper_limit [upper_limit downto bottom_limit  ] generate
       begin
             -statements
             -statements       
        end generate;

Example 1

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PARITY is
        Port (  input                 :  in  STD_LOGIC_VECTOR (7 downto 0);
                    output_even   : out  STD_LOGIC;
                    output_odd     : out STD_LOGIC);
        end PARITY;    
architecture Behavioral of PARITY is   
       function Parity_odd(input:STD_LOGIC_VECTOR (7 downto 0)) return std_logic is
               variable temp: std_logic:='0';
       begin
               for I in 0 to 7 loop
                     temp:=temp xor input(I);
               end loop;
               return (not temp);
       end Parity_odd;  
       function Parity_even(input:STD_LOGIC_VECTOR (7 downto 0)) return std_logic is
             variable temp: std_logic:='0';
       begin
             for I in input'range loop
                      temp:=temp xor input(I);
             end loop;
              return temp;
       end Parity_even;
begin
     output_even <=Parity_even(input);
     output_odd<=Parity_odd(input);
end Behavioral;

After the ModelSim simulation of the program, we obtain the following graph.

1


Example 2
(Converter)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity cevirici is
      Port ( input   : in    STD_LOGIC_VECTOR (7 downto 0);
                output  : out  STD_LOGIC_VECTOR (7 downto 0));
end cevirici;
architecture
Behavioral of cevirici is
begin
     U1: for I in 0 to 7 generate
     begin
          output(I)<=input(7-I);
     end generate;
end Behavioral;

After the ModelSim simulation of the program, we obtain the following graph.

2

                                                                                                           

    

                                                                                                                                    

 

                                                                                                                                                                                                                                                                   

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