FPGA Center



FUNCTION

Function is a sub-program consists of statements that return a value. The function contains only input parameters. Does not contain output parameters. Each function returns onlya value.

Syntax:   

function function_name (input1 : type, input2 : type,...) return  type is
      constant and variable declarations (signal declaration is not allowed)
begin
      function body
end function_name ;

Function Declaration:  

function function_name (input1 : type, input2 : type,...) return  type is

Function Instantiation:

signal <= function_name (input1 : type, input2 : type,...);

If you want to instantiate inputs with different order than the sequence in parentheses, you can use the following expression:

signal = function_name (input1 => insig1, input2 => insig2, ...);

EXAMPLE 1 (Three-Input AND/OR Gate):

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity OR_AND is
         port( in0           :  in std_logic;
                  in1           :  in std_logic;
                  in2           :  in std_logic;
                 out_and   : out std_logic;
                 out_or      : out std_logic);
         end OR_AND;

architecture Behavioral of OR_AND is

--Function Body
function AND_GATE(in0,in1,in2:std_logic) return std_logic is
      variable temp:std_logic;
       begin  
             temp:=in0 and in1 and in2;
             return  temp;                
      end AND_GATE;

--Function Body
function OR_GATE(in0,in1,in2:std_logic) return std_logic is
     begin  
         return in0 OR in1 OR in2;                   
      end OR_GATE;

begin
----Function instantiation in the program
      out_and<=AND_GATE(in0,in1,in2);
       out_or<=OR_GATE(in0,in1,in2);
end Behavioral;

After the ModelSim simulation of the program, we obtain the following graph.

1

EXAMPLE 2 (PARITY)

library IEEE;
use
IEEE.STD_LOGIC_1164.ALL;

entity Parityh is
     Port (input :  in  STD_LOGIC_VECTOR (8 downto 0);
               output : out  STD_LOGIC);
end Parityh;

architecture Behavioral of Parityh is
      function PARITY(X:std_logic_vector) return std_logic is
         variable temp:std_logic:='0';
     begin  
          for I in X'range loop
               temp:= temp XOR X(I);
         end loop;          
         return  temp;                        
     end PARITY;
begin
     output<=PARITY(input);
end Behavioral;

After the ModelSim simulation of the program, we obtain the following graph.

2

                                                                                                           

    

                                                                                                                                    

 

                                                                                                                                                                                                                                                                   

Home | Fpga | VHDL | VHDL Dictionary | Digital Design | Simulation | PCB | Examples | Contact Us
Copyright © 2010 - 2013 FPGAcenter. All Rights Reserved.