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GENERATE

It is possible to group similar components together under a single component and to define and repeat them by using "generate". VHDL design becomes simpler with generates.

1) FOR GENERATE

Label : for parameter in range generate
---declarations
begin
 --concurrent_statements
end generate Label ;

2) IF GENERATE

Label : if condition generate
   ---declarations
begin
   -- concurrent_statements
end generate Label ;

NOTE:

EXAMPLE 1 (OR GATE)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity or_gate is
    Port ( in1     : in STD_LOGIC_VECTOR (7 downto 0);
              in2      : in STD_LOGIC_VECTOR (7 downto 0);
             output :out STD_LOGIC_VECTOR (7 downto 0));
end or_gate;

architecture Behavioral of or_gate is
begin
  U1:for i in in1'range generate
              output(i)<=in1(i) or in2(i);
        end generate U1;
end Behavioral;

After the ModelSim simulation of the program, we obtain the following graph.

1

EXAMPLE 2 (BINARY COUNTER)

3

--FLIP-FLOP

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity D_FF is
    Port ( CLK : in STD_LOGIC;
               D      : in STD_LOGIC;
               Q      : out STD_LOGIC:='1';
               Q_n : out STD_LOGIC:='0');
end D_FF;

architecture Behavioral of D_FF is
begin
    process(CLK)
    begin
        if CLK='1' and CLK'event then
              Q<=D;
              Q_n<= not D;
         end if;
     end process;
end Behavioral;

--Binary Counter

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Binary_counter is
     generic(capacity:integer:=5);
     Port ( CLK           : in STD_LOGIC;
                 OUTPUT : out STD_LOGIC_VECTOR ((capacity-1) downto 0));
end Binary_counter;

architecture Behavioral of Binary_counter is

COMPONENT D_FF
      PORT(
                   CLK : IN std_logic;
                    D     : IN std_logic;
                    Q     : OUT std_logic;
                    Q_n : OUT std_logic  );
    END COMPONENT;

signal X:STD_LOGIC_VECTOR (capacity downto 0);
begin
    X(0)<=CLK;
    U1:for I in 0 to capacity-1 generate
     L1: D_FF PORT MAP(
                                            CLK => X(I),
                                             D => X(I+1),
                                             Q => OUTPUT(I),
                                             Q_n => X(I+1) );
         end generate;
end Behavioral;

After the ModelSim simulation of the program, we obtain the following graph.

2

                                                                                                           

    

                                                                                                                                    

 

                                                                                                                                                                                                                                                                   

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