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Generic is an optional VHDL structure which is used to transfer some of the parameters of the components to an entity.
Components which have the same basic structure like bus and signal size, can be used in different designs by using generics.

Generics can be declared in blocks, entities or components.

Unlike constants; generics can be declared in components or configurations and can be changed from the outside.

generic ( generic_aray羹z_listesi ) ;

NOTE: Generics which are in integer type are supported by most of the synthesis tools.


entity CPU is
     generic (BusWidth : Integer := 16);
     port(DataBus : inout Std_Logic_Vector(BusWidth-1 downto 0));
. . .

parametreler kullan覺c覺 taraf覺ndan tek bir noktadan deitirilebiliyor. In this example, the size of DataBus port is defined by generic. This generic can be used in all architectures which are related to CPU entity. In this way,all the parameters in whole design can be changed by the user at once.


entity Gen_Gates is
     generic (Delay : Time := 10 ns);
     port (In1, In2 : in Std_Logic;
                Output : out Std_Logic);
end Gen_Gates;
architecture Gates of Gen_Gates is
   . . .
   Output <= In1 or In2 after Delay;
   . . .
end Gates;

In this example delay generic determines the delay time of output.


Generics, provide static information to block structures and can be processed in architecture like constants. Unlike constants they can feed from the outside. Generics can be declared in entity and components. So generics are similar to the ports. However generics are always written before the ports.

Values which are determined by the generics in entity, can be read either in entity or in architecture related with the entity. Generics generally used as follows:






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