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PORT  

There are three types of most common used ports.

1. INPUT

  Port_name: in type;
  Data: in STD_LOGIC;

2. OUTPUT

  Port_name: out type;
  Output : out STD_LOGIC_VECTOR(3  downto 0);
  Output : out STD_LOGIC_VECTOR(0  to 3);

3. INOUT

This port can be used as both input and output. It's useful for databuses of data storage applications such as RAMs.

Port_name : inout type;

Example (RAM Application):

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity RAM is
    Port ( Clk : in  STD_LOGIC;          
               Data : inout  STD_LOGIC_VECTOR (7 downto 0);
               Adress : in  STD_LOGIC_VECTOR  (7 downto 0);
               R_Wn : in  STD_LOGIC);        
end RAM;

architecture Behavioral of RAM is
       type RAM_D is array (2**8-1 downto 0)  of std_logic_vector(7 downto 0);
       signal RAM_U : RAM_D;
 begin
        process(Clk,R_Wn)
        begin   
             if (falling_edge(Clk)) then --On the falling edge of he clock signal.
                      if R_Wn= '1' then --Read data from RAM.
                                Data<= RAM_U(conv_integer( Adress));
                       else --Write data to RAM.
                                RAM_U(conv_integer( Adress))<=Data;
                       end if;                          
              end if;

         end process;
   end Behavioral;

 

 

                                                                                                           

    

                                                                                                                                    

 

                                                                                                                                                                                                                                                                   

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