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RANGE

Range is used to determine sub sets of numerical values.

range lower_limit to upper_limit
range upper_limit downto lower_limit
range <> (unconstraint)

NOTE:

EXAMPLE 1 :

1 to 100 --Range is ascending from1 to 100 (including 1 and 100)
9 downto 0 --Range is descending from9 to 0 (including 9 and 0)
15 to 0    --Range is null. Because downto must be used in order to define a range from 15 to 0.

EXAMPLE 2 :

type Memo is array (NATURAL range <>) of Bit_Vector(7 downto 0);
--An unconstraint memory which has 8-bits arrays has been defined with the expressions above.

mem

signal memory_ram : Bellek (11 downto 1); 
--The capacity of the memory is limited with this expression.


EXAMPLE 3 (10x8 MEMORY):

This program will create a 11x8 memory. The controller of the program is RESET ve RW (read_write). If RW=1, program will behave in READ mode. If RW=0, WRITE mode is activated. RESET will be used to clear memory.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity MEMORY is
Port ( CLK : in STD_LOGIC;
           input : inout BIT_VECTOR (7 downto 0);
           RW : in STD_LOGIC;
           reset: in STD_LOGIC);
end MEMORY;

architecture Behavioral of MEMORY is
     type Memory is array (natural range<> ) of bit_vector(7 downto 0);
     signal memory_ram : Memory(11 downto 1);
begin
process(clk,reset)
     variable counter:integer:=0;
begin
      if reset='1' then
              for i in memory_ram'range loop
                    memory_ram(i)<=(others=>'0');
                    counter:=0;
               end loop;
      elsif clk='1' and clk'event then
            if rw= '0' then
                  counter:=counter+1;
                  memory_ram(counter)<=input;
            else
                 input <= memory_ram(counter);
                 counter:=counter-1;
            end if;
            if counter= 12 then
                  counter:= 11;
            end if;
            if counter=0 then
                  counter := 1;
            end if;
         end if;
     end process;
end Behavioral;

Test Bench:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE
IEEE.std_logic_arith.all;

ENTITY memory_test_bench IS
END memory_test_bench;

ARCHITECTURE behavior OF memory_test_bench IS

--Component Declaration for the Unit Under Test (UUT)
COMPONENT MEMORY
PORT(CLK : INstd_logic;
            input : INOUTstd_logic_vector(7 downto 0);
            RW : INstd_logic;
            reset : INstd_logic );
END COMPONENT;

--Inputs
signal CLK : std_logic := '0';
signal RW : std_logic := '0';
signal RESET : std_logic := '0';

signal input : std_logic_vector(7 downto 0);
constant clk_period:time := 10 ns;

BEGIN

CLK<= not CLK after clk_period/2;

stim_proc: process
   begin
      RW<='0';
      for i in 0 to 10 loop
         input<=CONV_STD_LOGIC_VECTOR(i, 8);
      wait for clk_period;
      end loop;
      wait for clk_period*5;
         RESET<='1';
      wait for clk_period;
         RESET<='0';
      for i in 10 downto 10 loop
         input<=CONV_STD_LOGIC_VECTOR(i, 8);
      wait for clk_period;
      end loop;
      wait for clk_period*5;
      RW<='1';
      wait for clk_period*10;
      assert false
      report "SIMULATION COMPLETED "
      severity failure;
 end process;
END;

 

 

                                                                                                           

    

                                                                                                                                    

 

                                                                                                                                                                                                                                                                   

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