Signals are wires between the inner blocks of a hardware design.
entity Transmit is
port (Data : Std_Logic_Vector(15 downto 8));
end entity Transmit;
architecture ARC of Transmit is
signal SC : Std_Logic;
signal Flag1, Flag2 : Bit;┬á -- Signals that have the same type are declared together
Data (8-bit vector) is declared as a port in the entity. Flag1, Flag2 and SC signals are used in the architecture called ARC.
type myType is ('X','0','1','Z');
signal S1 : myType; -- 'X' which is the left most value of myType is assigned to S1.
signal S2 : myType := 'X';┬á -- Assignment is not needed. It is similar with he previous line.
signal S3 : myType := '1';
Signals are parallel comunication lines which determines the system characteristics. Signals attributes are used to access all signal parameters. Each signal can have a past, present and future values.
Signals can be declared in package, architecture or block.
Signals that are in a package can be used in all designs which are related to that package provided that "use" expression is writen.
Ports declared in entity, means that signals for every achitecture related to that entity.┬á(EXAMPLE1)
A signal declaration can have more than one identifiers. In that case, each identifiers refers to separate signals.
First value can be assigned to a signal provided that he value has same type with signal. If there is no first assignment, the left most value of the declared type becomes the first value of the signal automatically. (EXAMPLE2)