FPGA Center



VARIABLE DECLARATION

Variable is an object that can have d┼čfferent values.

variable variable_name : type;
variable variable_name: type := first_value;

NOTE:

EXAMPLE 1:

type Memory is array (Natural range <>, Natural range <>) of Std_Logic; --Unconstraint array
variable Delay1, Delay2 : Time;                         --Varibles with same type are listed in the same line.
variable RAM1: Memory (0 to 1023, 0 to 8);  --1KB memory capacity is assigned.

Although memory is not constraint at declaraiton, it is constraied with the range of natural subtype. RAM is constrained as 1 KB (1024x8 bits) capacity.

EXAMPLE 2:

type Memory is array (Natural range <>, Natural range <>) of Std_Logic;
variable Error : Boolean := true;┬á                --The first value s assigned as True.
variable RAM2 : Memory (0 to 7, 0 to 7):=   -- Memory is cleared with aggregate method.
  (('0', '0', '0', '0', '0', '0', '0', '0'),
  ('0', '0', '0', '0', '0', '0', '0', '0'),
  ('0', '0', '0', '0', '0', '0', '0', '0'),
  ('0', '0', '0', '0', '0', '0', '0', '0'),
  ('0', '0', '0', '0', '0', '0', '0', '0'),
  ('0', '0', '0', '0', '0', '0', '0', '0'),
  ('0', '0', '0', '0', '0', '0', '0', '0'),
  ('0', '0', '0', '0', '0', '0', '0', '0'));

EXAMPLE 3:

variable A : BIT;
variable B : INTEGER;
variable C,D : REAL;
variable E, F : BIT_VECTOR (0 to 3);

 

                                                                                                           

    

                                                                                                                                    

 

                                                                                                                                                                                                                                                                   

Home | Fpga | VHDL | VHDL Dictionary | Digital Design | Simulation | PCB | Examples | Contact Us
Copyright © 2010 - 2013 FPGAcenter. All Rights Reserved.