FPGA Center



WHEN-ELSE

"When" is used with "else" expression in order to chose concurrent conditional statments.

variable <= statement when condition else
                        statement when condition else
                        statement ;

EXAMPLE

A 3-input and 1-output module is designed in this example. Relation between inputs and output of this module as follows:

1

library IEEE;
use
IEEE.STD_LOGIC_1164.ALL;
entity WHEN_ELSE is
     Port ( in1 : in STD_LOGIC;
                in2 : in STD_LOGIC;
                in3 : in STD_LOGIC;
                output : out STD_LOGIC_VECTOR (1 downto 0));
end WHEN_ELSE;

architecture Behavioral of WHEN_ELSE is
    begin
        output<= "00" when in1='0' else
                          "01"when in2='0' else
                          "10"when in3='0' else
                          "11";
end Behavioral;

After simulation on ModelSim, we get the plot below:

2

 

 

                                                                                                           

    

                                                                                                                                    

 

                                                                                                                                                                                                                                                                   

Home | Fpga | VHDL | VHDL Dictionary | Digital Design | Simulation | PCB | Examples | Contact Us
Copyright © 2010 - 2013 FPGAcenter. All Rights Reserved.